This invention relates to design and synthesis of synchronous digital circuits.
Hardware description languages (HDLs) have been used for some time to design electronic circuits, and in particular to design synchronous (clocked) digital circuits. One class of hardware description languages are “register-transfer languages” (RTLs) in which the circuit has, or is abstracted to have, a set of registers, and the language specifies the values of the registers in each clock period in terms of the values in the previous clock period. A widely used HDL is Verilog, which has been standardized as IEEE standard 1364-1995, and for which numerous software tools are available. Verilog supports a variety of specification approaches, including a RTL approach.
Design of complex digital circuits, such as pipelined and superscalar processors, using an RTL approach typically requires a hardware architect to specify the overall functionality of the system which can be defined in terms of modular components that are defined separately, as well as specify the correct coordination of concurrent processing modules in the circuit. As hardware systems become more complex, for example pipelined processors which allow out-of-order and speculative instruction execution, this task is increasingly time consuming and is subject to human error.
Other HDL approaches attempt to specify a digital circuit in “behavioral” terms, without necessarily identifying the structure of the underlying circuit. For instance, Verilog supports such a behavioral specification approach. However, it is not always possible or feasible to synthesize an equivalent digital circuit from such a behavioral specification.
A variety of software tools are available for processing HDL specifications, including tools for simulating the specified circuits. Formal verification of the correctness of an HDL specification is often difficult, or even impossible, due in part to the nature and complexity of the specification.